View EM42AM1684LBA-75FE_5067053.PDF datasheet online --- IC-ON-LINE

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Features
* Internal Double-Date-Rate architecture with 2 Accesses per clock cycle. * 1.8V 0.1V VDD/VDDQ * 1.8V LV-COMS compatible I/O * Burst Length (B/L) of 2, 4, 8, 16 * 3 Clock read latency (CL3) * Bi-directional,intermittent data strobe(DQS) * All inputs except data and DM are sampled at the positive edge of the system clock. * Data Mask (DM) for write data * Sequential & Interleaved Burst type available * Auto Precharge option for each burst accesses * DQS edge-aligned with data for Read cycles * DQS center-aligned with data for Write cycles * No DLL;CK to DQS is not synchronized * Deep power down mode * Partial Array Self-Refresh(PASR) * Auto Temperature Compensated Self-Refresh (TCSR) by built-in temperature sensor * Auto Refresh and Self Refresh * 8,192 Refresh Cycles / 64ms
EM42BM1684LBA
512Mb (8Mx4Bankx16) Double DATA RATE SDRAM
Description
The EM42BM1684LBA is high speed Synchronous graphic RAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as 8Meg words x 4 banks by 16 bits. The 512Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and It transfers the datafor both rising and falling edges of the system clock.It means the doubled data bandwidth can be achieved at the I/O pins. Available packages:FBGA-60B(12mmx10mm).
Ordering Information
Part No
EM42BM1684LBA-75F EM42BM1684LBA-75FE
Organization
32M X 16 32M X 16
Max. Freq
133MHz/DDR266 @CL3 133MHz/DDR266 @CL3
Package
BGA-60B BGA-60B
Grade
Commercial. Extend Temp.
Pb
Free Free
* EOREX reserves the right to change products or specification without notice.
Jul. 2006 1/20 www.eorex.com
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Pin Assignment
1 VSSQ DQ14 DQ12 DQ10 DQ8 NC 2 DQ15 VDDQ VSSQ VDDQ VSSQ VSS CLK A12 A11 A8 A6 A4 3 VSS DQ13 DQ11 DQ9 UDQS UDM /CLK CKE A9 A7 A5 VSS A B C D E F G H J K L M 7 VDD DQ2 DQ4 DQ6
EM42BM1684LBA
8 DQ0 VSSQ VDDQ VSSQ VDDQ VDD /CAS /CS BA0 A10/AP A1 A3
9 VDDQ DQ1 DQ3 DQ5 DQ7 NC
LDQS LDM /WE /RAS BA1 A0 A2 VDD
60ball FBGA / (12mm x 10mm x 1.2mm)
Jul. 2006 2/20
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Pin Description (Simplified)
Pin Name G2,G3 CLK,/CLK
EM42BM1684LBA
Function (System Clock) Clock input active on the Positive rising edge except for DQ and DM are active on both edge of the DQS. CLK and /CLK are differential clock inputs. (Chip Select) /CS enables the command decoder when "L" and disable the command decoder when "H".The new command are overLooked when the command decoder is disabled but previous operation will still continue. (Clock Enable) Activates the CLK when "H" and deactivates when "L". When deactivate the clock,CKE low signifies the power down or self refresh mode. (Address) Row address (A0 to A12) and Calumn address (CA0 to CA9) are multiplexed on the same pin. CA10 defines auto precharge at Calumn address. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS "L". Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output) Data Inputs and Outputs are synchronized with both edge of DQS. (Data Input/Output Mask) DM controls data inputs.LDM corresponds to the data on DQ0~DQ7.UDM corresponds to the data on DQ8~DQ15........ (Data Input/Output) Data inputs and outputs are multiplexed on the same pin. (Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection/Reserved for Future Use) This pin is recommended to be left No Connection on the device.
H8
/CS
H1
CKE
K7,L8,L7,M8,M2, L3,L2,K3,K2,J3,K8, J2,H2 J8,J7 H7
A0~12
BA0, BA1 /RAS
G8
/CAS
G7 E7,E3 F7,F8 A8,B9,B7,C9 C7,D9,D7,E9 E1,D3,D1,C3 C1,B3,B1,A2 A7,F8,M7/ A3,F2,M3 A9,B1,C8,D2,E8 / A1,B8,C2,D8,E2, F1,F9
/WE LDQS, UDQS LDM,UDM
DQ0~15
VDD/VSS VDDQ/VSSQ NC/RFU
Jul. 2006 3/20
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Absolute Maximum Rating
Symbol VIN, VOUT VDD, VDDQ TOP TSTG PD Item Input, Output Voltage Power Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation
EM42BM1684LBA
Rating -0.5 ~ +2.3 -0.5 ~ +2.3 Commercial 0 ~ +70 Extended -25 ~ +85 -55 ~ +125 1
Units V V C C W
IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Capacitance (VCC=1.8V 0.1V, f=1MHz, TA=25C)
Symbol CCLK CI CO Parameter Clock Capacitance Input Capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU Input/Output Capacitance Min. 2.0 2.0 3.5 Typ. Max. 4.5 4.5 6.0 Units pF pF pF
Recommended DC Operating Conditions (TA=0C ~70C)
Symbol VDD VDDQ VIH Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input Logic High Voltage Min. 1.7 1.7 0.8* VDDQ -0.3 Typ. 1.8 1.8 Max. 1.9 1.9 VDDQ+0.3 0.2*VDDQ Units V V V V
VIL Input Logic Low Voltage Note: * All voltages referred to VSS.
Jul. 2006 4/20
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Recommended DC Operating Conditions
(VDD=1.8V0.1V, TA=0C ~ 70C) Symbol IDD1 IDD2P Parameter Operating Current
(Note 1)
EM42BM1684LBA
Test Conditions Burst length=2, tRCtRC(min.), IOL=0mA, One bank active CKEVIL(max.), tCK=min CKEVIL(min.), tCK=min, /CSVIH(min.) Input signals are changed one time during 2 clks CKEVIL(max.), tCK=min CKEVIH(min.), tCK=min, /CSVIH(min.) Input signals are changed one time during 2 clks tCK tCK(min.), IOL=0mA, All banks active tRC tRFC (min.), All banks active CKE0.2V
Max. -75 70 1
Units mA mA
Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non-power Down Mode Operating Current (Burst (Note 2) Mode) Refresh Current
(Note 3)
IDD2N
4
mA
IDD3P
3
mA
IDD3N
10
mA
IDD4 IDD5 IDD6
140 100 0.8
mA mA mA
Self Refresh Current
*All voltages referenced to VSS. Note 1: IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics.
Recommended DC Operating Conditions (Continued)
Symbol IIL IOL VOH VOL Parameter Input Leakage Current Output Leakage Current High Level Output Voltage Low Level Output Voltage Test Conditions 0VIVDDQ, VDDQ=VDD All other pins not under test=0V 0VOVDDQ, DOUT is disabled IO=-0.1mA IO=+0.1mA Min. -2 -1.5 0.9*VDDQ 0.1*VDDQ Typ. Max. +2 +1.5 Units uA uA V V
Jul. 2006 5/20
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Block Diagram
Auto/ Self Refresh Counter
EM42BM1684LBA
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 Col. Add. Buffer S/ A & I/ O Gating Col. Decoder Data Out DOi Data In DM
Memory Array
Write DQM Control
Mode Register Set
Col Add. Counter Burst Counter
Timing Register
/CLK
CLK
CKE
/CS
/ RAS
/ CAS
/ WE
DM
DQS
Jul. 2006 6/20
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AC Operating Test Conditions
(VDD=1.8V 0.1V, TA=0C ~70C) Item Output Reference Level Output Load Input Signal Level Transition Time of Input Signals Input Reference Level
EM42BM1684LBA
Conditions 0.9V/0.9V See diagram as below 1.6V/0.2V 0.5ns 0.9V
AC Operating Test Characteristics
(VDD=1.8V0.1V, TA=0C ~70C) Symbol tDQCK tDQSCK tCL,tCH tCK tDH,tDS tDIPW tHZ,tLZ tDQSQ tDQSS tDSL,tDSH tMRD tWPRES tWPST tIH,tIS tRPRE Parameter DQ output access from CLK,/CLK DQS output access from CLK,/CLK CL low/high level width Clock Cycle Time DQ and DM hold/setup time DQ and DM input pulse width for each input Data out high/low impedance time from CLK,/CLK DQS-DQ skew for associated DQ signal Write command to first latching DQS transition DQS input valid window Mode Register Set command cycle time Write Preamble setup time Write Preamble Address/control input hold/setup time Read Preamble -7.5 Min. Max. 2 2 0.45 7.5 0.8 1.75 1 0.75 0.2 2 0 0.4 1.3 0.9 6 6 0.55 6 0.65 1.25 0.6 1.1 Units ns ns tCK ns ns ns ns ns tCK tCK tCK ns tCK ns tCK
Jul. 2006 7/20
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(VDD=1.8V0.1V, TA=0C ~70C) Symbol tRPST tRAS tRC tRFC tRCD tRP tRRD tCCD tHZP tCDLW tDPL tSREX tWTR tCKE tWPD tRPD tWRD tBSTW tWRD tREFI Parameter Read Postamble Active to Precharge command period Active to Active command period Auto Refresh Row Cycle Time Active to Read or Write delay Precharge command period Active bank A to B command period Column address to column address delay Pre-charge command to high-Z Last data in to Write command Last data in to Precharge command Exit self refresh to non-col. command Internal Write to Read command delay CKE minimum pulse width Write to pre-charge delay(same bank) Read to pre-charge delay(same bank) Write to Read command delay Burst stop to write delay Write recovery Average periodic refresh interval -75 Min. 0.4 45 75 108 30 22.5 15 1 3 1 3 16 1 2 3+BL/2 BL/2 2+BL/2 3 2 -
EM42BM1684LBA
AC Operating Test Characteristics (Continued)
Units Max. 0.6 120k 7.8 tCK ns ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK us
Jul. 2006 8/20
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Simplified State Diagram
EM42BM1684LBA
Jul. 2006 9/20
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1. Command Truth Table
Command Ignore Command No Operation Burst Stop Read Read with Auto Pre-charge Write Write with Auto Pre-charge Bank Activate Pre-charge Select Bank Pre-charge All Banks Symbol DESL NOP BSTH READ READA WRIT WRITA ACT PRE PALL CKE n-1 n HX H H H H H H H H H X X X X X X X X X /CS H L L L L L L L L L X H H H H H L L L L
EM42BM1684LBA
BA0, BA1 X X X V V V V V V X
/RAS
/CAS X H H L L L H H H H
/WE X H L H H L H H L L
A10 X X X L H L H V L H L
A12~A0 X X X V V V V V X X V
Mode Register Set MRS HX L L L L L H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
2. CKE Truth Table
Item Idle Idle Self Refresh Idle Command CBR Refresh Command Self Refresh Entry Self Refresh Exit Power Down Entry Symbol REF SELF CKE n-1 n HH H L L H L H H L /CS L L L H X /RAS L L H X X X /CAS L L H X X X /WE H H H X X X Addr. X X X X X X
Power Down Power Down Exit L H X Remark H = High level, L = Low level, X = High or Low level (Don't care)
Jul. 2006 10/20
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3. Operative Command Table
Current State /CS
H L L L Idle L L L L H L L Row Active L L L L L H L L L Read L L L L H L L L L L L L X H H H H H L L X H H L H L H L X H L H BA/RA BA, A10 X Op-Code, Mode-Add X X X BA/CA/A10 ACT PRE/PREA REFA MRS DESL NOP TERM READ/READA
EM42BM1684LBA
/R
X H H H L L L L X H H H L L L L X H H H
/C
X H H L H H L L X H H L H H L L X H H L
/W
X H L X H L H L X H L L H L H L X H L H
Addr.
X X X BA/CA/A10 BA/RA BA, A10 X Op-Code, Mode-Add X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10
Command
DESL NOP TERM READ/WRIT/BW ACT PRE/PREA REFA MRS DESL NOP READ/READA WRIT/WRITA ACT PRE/PREA REFA MRS DESL NOP TERM READ/READA
Action NOP NOP NOP ILLEGAL
(Note 1)
Bank active,Latch RA NOP (Note 4) Auto refresh Mode register NOP NOP Begin read,Latch CA, Determine auto-precharge Begin write,Latch CA, Determine auto-precharge ILLEGAL Precharge/Precharge all ILLEGAL ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) Terminal burst Terminate burst,Latch CA, Begin new read, Determine Auto-precharge ILLEGAL
(Note 1) (Note 1) (Note 3)
Terminate burst, PrecharE ILLEGAL ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL Terminate burst with DM="H",Latch CA,Begin read,Determine (Note 2) auto-precharge Terminate burst,Latch CA,Begin new write, Determine (Note 2) auto-precharge ILLEGAL
(Note 1)
Write
L L L L L
H L L L L
L H H L L
L H L H L
BA/CA/A10 BA/RA BA, A10 X Op-Code,
WRIT/WRITA ACT PRE/PREA REFA MRS
Terminate burst with DM="H", Precharge ILLEGAL ILLEGAL
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Jul. 2006 11/20
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Current State /CS
H L L L Read with AP L L L L H L L L Write with AP L L L L H L L L Pre-charging L L L L H L L L Row Activating L L L L
EM42BM1684LBA
3. Operative Command Table (Continued)
/R
X H H H L L L L X H H H L L L L X H H H L L L L X H H H L L L L
/C
X H H L H H L L X H H L H H L L X H H L H H L L X H H L H H L L
/W
X H L X H L H L X H L X H L H L X H L X H L H L X H L X H L H L
Addr.
X X BA/CA/A10 BA/RA BA/A10 X X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add
Command
DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS
Action NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL (Note 1) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL (Note 1) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(idle after tRP) NOP(idle after tRP) NOP (Note 1) ILLEGAL ILLEGAL (Note 3) NOP(idle after tRP) ILLEGAL ILLEGAL NOP(Row active after tRCD) NOP(Row active after tRCD) NOP (Note 1) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
(Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
Jul. 2006 12/20
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Current State /CS
H L L L Write Recovering L L L L L H L L L L L L L
EM42BM1684LBA
3. Operative Command Table (Continued)
/R
X H H H H L L L L X H H H L L L L
/C
X H H L L H H L L X H H L H H L L
/W
X H L H L H L H L X H L X H L H L
Addr.
X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add
Command
DESL NOP TERM READ WRIT/WRITA ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRIT ACT PRE/PREA REFA MRS
Action NOP NOP NOP (Note 1) ILLEGAL New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(idle after tRP) NOP(idle after tRP) NOP ILLEGAL ILLEGAL NOP(idle after tRP) ILLEGAL ILLEGAL
(Note 1) (Note 1)
Refreshing
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 1: ILLEGAL to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 2: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 3: NOP to bank precharging or in idle state.May precharge bank indicated by BA. Note 4: ILLEGAL of any bank is not idle.
Jul. 2006 13/20
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4. Command Truth Table for CKE
Current State CKE n-1 n
H L L L L L L H L L L L L L H H H H H H H H H L Any State Other than Listed above H X H H H H H L X H H H H H L H L L L L L L L L X H
EM42BM1684LBA
/CS
X H L L L L X X H L L L L X X H L L L L L L L X X
/R
X X H H H L X X X H H H L X X X H H H L L L L X X
/C
X X H H L X X X X H H L X X X X H H L H L L L X X
/W
X X H L X X X X X H L X X X X X H L X H H L L X X
Addr.
X X X X X X X X X X X X X X X X X X X RA X Op-Code Op-Code X X
Action INVALID Exist Self-Refresh Exist Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP(Maintain self refresh) INVALID Exist Power down Exist Power down ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power down) Refer to function true table (Note 3) Enter power down mode (Note 3) Enter power down mode ILLEGAL ILLEGAL Row active/Bank active (Note 3) Enter self-refresh Mode register access Special mode register access Refer to current state Refer to command truth table
Self Refresh
Both bank precharge power down
All Banks Idle
Remark: H = High level, L = Low level, X = High or Low level (Don't care) Notes 1: After CKE's low to high transition to exist self refresh mode.And a time of tRC(min) has to be Elapse after CKE's low to high transition to issue a new command. Notes 2:CKE low to high transition is asynchronous as if restarts internal clock. Notes 3:Power down and self refresh can be entered only from the idle state of all banks.
Jul. 2006 14/20
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Mode Register Definition Mode Register Set
EM42BM1684LBA
The mode register stores the data for controlling the various operating modes of DDR SDRAM which contains addressing mode, burst length, /CAS latency, test mode, DLL reset and various vendors specific opinions. The defaults values of the register is not defined, so the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0 ( The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. ) The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS latency ( read latency from column address ) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset. A7 must be set to low for normal MRS operation.
Jul. 2006 15/20
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Address input for Mode Register Set
EM42BM1684LBA
Jul. 2006 16/20
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Burst Type (A3)
Burst Length 2 A3 X X X 4 X X X X X X 8 X X X X X 0 0 0 0 0 0 0 16 0 1 1 1 1 1 1 1 1 A2 X X X X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456
EM42BM1684LBA
Sequential Addressing
Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 2 3 0 1 6 7 4 5 10 11 8 9 14 15 12 13 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 4 5 6 7 0 1 2 3 12 13 14 15 8 9 10 11 5 4 7 6 1 0 3 2 13 12 15 14 9 8 11 10 6 7 4 5 2 3 0 1 14 15 12 13 10 11 8 9 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 9 8 11 10 13 12 15 14 1 0 3 2 5 4 7 6 10 11 8 9 14 15 12 13 2 3 0 1 6 7 4 5 11 10 9 8 15 14 13 12 3 2 1 0 7 6 5 4 12 13 14 15 8 9 10 11 4 5 6 7 0 1 2 3 13 12 15 14 9 8 11 10 5 4 7 6 1 0 3 2 14 15 12 13 10 11 8 9 6 7 4 5 2 3 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* Page length is a function of I/O organization and column addressing
Jul. 2006 17/20
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Extended Mode Register Set ( EMRS )
EM42BM1684LBA
The Extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA1 ( The DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation.
Jul. 2006 18/20
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Output Drive Strength
EM42BM1684LBA
The normal drive strength got all outputs is specified to be LV-CMOS. By setting EMRS specific parameter on A6 and A5, driving capability of data output drivers is selected.
Temperature Compensated Self-Refresh
TCSR controlled by programming in the extended mode register (EMRS). The memory automatically changes the self-refresh cycle by temperature fluctuations.
Partial Array Self Refresh
In EMRS setting ,memory array size to be refreshed during self-refresh operation is programmable in order to reduce power. Data outside the defined area will not be retained during self-refresh.
Jul. 2006 19/20
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Package Description
(60 balls; 0.8mmx1.0mm Pitch; FBGA Package)
EM42BM1684LBA
Jul. 2006 20/20
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